 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_wm.c,v 1.508.4.54 2024/02/03 12:04:06 martin Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.508.4.55 2024/02/29 10:46:27 martin Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -72,27 +72,27 @@
+ *
  * TODO (in order of importance):
+ *
  *	- Check XXX'ed comments
  *	- TX Multi queue improvement (refine queue selection logic)
  *	- Split header buffer for newer descriptors
  *	- EEE (Energy Efficiency Ethernet)
  *	- Virtual Function
  *	- Set LED correctly (based on contents in EEPROM)
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.508.4.54 2024/02/03 12:04:06 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.508.4.55 2024/02/29 10:46:27 martin Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #include "opt_if_wm.h"
 #endif
 #include <sys/param.h>
 #include <sys/callout.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/errno.h>
 #include <sys/interrupt.h>
 #include <sys/ioctl.h>
 @@ -459,29 +459,29 @@ struct wm_rxqueue {
 	int rxq_len;
 	struct mbuf *rxq_head;
 	struct mbuf *rxq_tail;
 	struct mbuf **rxq_tailp;
 	bool rxq_stopping;
 	uint32_t rxq_packets;		/* for AIM */
 	uint32_t rxq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	/* RX event counters */
 	WM_Q_EVCNT_DEFINE(rxq, intr);	/* Interrupts */
 	WM_Q_EVCNT_DEFINE(rxq, defer);	/* Rx deferred processing */
 	WM_Q_EVCNT_DEFINE(rxq, ipsum);	/* IP checksums checked */
 	WM_Q_EVCNT_DEFINE(rxq, tusum);	/* TCP/UDP cksums checked */
 	WM_Q_EVCNT_DEFINE(rxq, qdrop);	/* Rx queue drop packet */
 #endif
 };
 struct wm_queue {
 	int wmq_id;			/* index of TX/RX queues */
 	int wmq_intr_idx;		/* index of MSI-X tables */
 	uint32_t wmq_itr;		/* interrupt interval per queue. */
 	bool wmq_set_itr;
 	struct wm_txqueue wmq_txq;
 	struct wm_rxqueue wmq_rxq;
 	char sysctlname[32];		/* Name for sysctl */
 @@ -2683,26 +2683,30 @@ alloc_retry:
 	case WM_T_PCH_TGP:
 		apme_mask = WUC_APME;
 		eeprom_data = CSR_READ(sc, WMREG_WUC);
 		if ((eeprom_data & apme_mask) != 0)
 			sc->sc_flags |= WM_F_WOL;
 		break;
 	default:
 		break;
+	}
 	/* Reset the chip to a known state. */
 	wm_reset(sc);
 	/* sc->sc_pba is set in wm_reset(). */
 	aprint_verbose_dev(sc->sc_dev, "RX packet buffer size: %uKB\n",
 	    sc->sc_pba);
 	/*
 	 * Check for I21[01] PLL workaround.
+	 *
 	 * Three cases:
 	 * a) Chip is I211.
 	 * b) Chip is I210 and it uses INVM (not FLASH).
 	 * c) Chip is I210 (and it uses FLASH) and the NVM image version < 3.25
 	 */
 	if (sc->sc_type == WM_T_I211)
 		sc->sc_flags |= WM_F_PLL_WA_I210;
 	if (sc->sc_type == WM_T_I210) {
 		if (!wm_nvm_flash_presence_i210(sc))
 			sc->sc_flags |= WM_F_PLL_WA_I210;
 @@ -6516,26 +6520,27 @@ teardown:
 	sysctl_teardown(log);
 err:
 	sc->sc_sysctllog = NULL;
 	device_printf(sc->sc_dev, "%s: sysctl_createv failed, rv = %d\n",
 	    __func__, rv);
+}
 static void
 wm_update_stats(struct wm_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	uint64_t crcerrs, algnerrc, symerrc, mpc, colc,  sec, rlec, rxerrc,
 	    cexterr;
 	uint64_t total_qdrop = 0;
 	crcerrs = CSR_READ(sc, WMREG_CRCERRS);
 	symerrc = CSR_READ(sc, WMREG_SYMERRC);
 	mpc = CSR_READ(sc, WMREG_MPC);
 	colc = CSR_READ(sc, WMREG_COLC);
 	sec = CSR_READ(sc, WMREG_SEC);
 	rlec = CSR_READ(sc, WMREG_RLEC);
 	WM_EVCNT_ADD(&sc->sc_ev_crcerrs, crcerrs);
 	WM_EVCNT_ADD(&sc->sc_ev_symerrc, symerrc);
 	WM_EVCNT_ADD(&sc->sc_ev_mpc, mpc);
 	WM_EVCNT_ADD(&sc->sc_ev_colc, colc);
 	WM_EVCNT_ADD(&sc->sc_ev_sec, sec);
 @@ -6664,26 +6669,42 @@ wm_update_stats(struct wm_softc *sc)
 		WM_EVCNT_ADD(&sc->sc_ev_debug4, CSR_READ(sc, WMREG_DEBUG4));
 		WM_EVCNT_ADD(&sc->sc_ev_rxdmtc, CSR_READ(sc, WMREG_RXDMTC));
 		WM_EVCNT_ADD(&sc->sc_ev_htcbdpc, CSR_READ(sc, WMREG_HTCBDPC));
 		WM_EVCNT_ADD(&sc->sc_ev_hgorc,
 		    CSR_READ(sc, WMREG_HGORCL) +
 		    ((uint64_t)CSR_READ(sc, WMREG_HGORCH) << 32));
 		WM_EVCNT_ADD(&sc->sc_ev_hgotc,
 		    CSR_READ(sc, WMREG_HGOTCL) +
 		    ((uint64_t)CSR_READ(sc, WMREG_HGOTCH) << 32));
 		WM_EVCNT_ADD(&sc->sc_ev_lenerrs, CSR_READ(sc, WMREG_LENERRS));
 		WM_EVCNT_ADD(&sc->sc_ev_scvpc, CSR_READ(sc, WMREG_SCVPC));
 		WM_EVCNT_ADD(&sc->sc_ev_hrmpc, CSR_READ(sc, WMREG_HRMPC));
 #ifdef WM_EVENT_COUNTERS
 		for (int i = 0; i < sc->sc_nqueues; i++) {
 			struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 			uint32_t rqdpc;
 			rqdpc = CSR_READ(sc, WMREG_RQDPC(i));
 			/*
 			 * On I210 and newer device, the RQDPC register is not
 			 * cleard on read.
 			 */
 			if ((rqdpc != 0) && (sc->sc_type >= WM_T_I210))
 				CSR_WRITE(sc, WMREG_RQDPC(i), 0);
 			WM_Q_EVCNT_ADD(rxq, qdrop, rqdpc);
 			total_qdrop += rqdpc;
+		}
 #endif
+	}
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc)) {
 		WM_EVCNT_ADD(&sc->sc_ev_tlpic, CSR_READ(sc, WMREG_TLPIC));
 		WM_EVCNT_ADD(&sc->sc_ev_rlpic, CSR_READ(sc, WMREG_RLPIC));
 		if ((CSR_READ(sc, WMREG_MANC) & MANC_EN_BMC2OS) != 0) {
 			WM_EVCNT_ADD(&sc->sc_ev_b2ogprc,
 			    CSR_READ(sc, WMREG_B2OGPRC));
 			WM_EVCNT_ADD(&sc->sc_ev_o2bspc,
 			    CSR_READ(sc, WMREG_O2BSPC));
 			WM_EVCNT_ADD(&sc->sc_ev_b2ospc,
 			    CSR_READ(sc, WMREG_B2OSPC));
 			WM_EVCNT_ADD(&sc->sc_ev_o2bgptc,
 			    CSR_READ(sc, WMREG_O2BGPTC));
 @@ -6692,43 +6713,45 @@ wm_update_stats(struct wm_softc *sc)
 	ifp->if_collisions += colc;
 	ifp->if_ierrors +=
 	    crcerrs + algnerrc + symerrc + rxerrc + sec + cexterr + rlec;
 	/*
 	 * WMREG_RNBC is incremented when there are no available buffers in
 	 * host memory. It does not mean the number of dropped packets, because
 	 * an Ethernet controller can receive packets in such case if there is
 	 * space in the phy's FIFO.
+	 *
 	 * If you want to know the nubmer of WMREG_RMBC, you should use such as
 	 * own EVCNT instead of if_iqdrops.
 	 */
-	ifp->if_iqdrops += mpc;
+	ifp->if_iqdrops += mpc + total_qdrop;
+}
 void
 wm_clear_evcnt(struct wm_softc *sc)
+{
 #ifdef WM_EVENT_COUNTERS
 	int i;
 	/* RX queues */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		WM_Q_EVCNT_STORE(rxq, intr, 0);
 		WM_Q_EVCNT_STORE(rxq, defer, 0);
 		WM_Q_EVCNT_STORE(rxq, ipsum, 0);
 		WM_Q_EVCNT_STORE(rxq, tusum, 0);
 		if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
 			WM_Q_EVCNT_STORE(rxq, qdrop, 0);
+	}
 	/* TX queues */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		int j;
 		WM_Q_EVCNT_STORE(txq, txsstall, 0);
 		WM_Q_EVCNT_STORE(txq, txdstall, 0);
 		WM_Q_EVCNT_STORE(txq, fifo_stall, 0);
 		WM_Q_EVCNT_STORE(txq, txdw, 0);
 		WM_Q_EVCNT_STORE(txq, txqe, 0);
 		WM_Q_EVCNT_STORE(txq, ipsum, 0);
 @@ -8042,29 +8065,30 @@ wm_alloc_txrx_queues(struct wm_softc *sc
 			break;
 		error = wm_alloc_rx_buffer(sc, rxq);
 		if (error) {
 			wm_free_rx_descs(sc, rxq);
 			break;
+		}
 #ifdef WM_EVENT_COUNTERS
 		xname = device_xname(sc->sc_dev);
 		WM_Q_INTR_EVCNT_ATTACH(rxq, intr, rxq, i, xname);
 		WM_Q_INTR_EVCNT_ATTACH(rxq, defer, rxq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(rxq, ipsum, rxq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(rxq, tusum, rxq, i, xname);
 		if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
 			WM_Q_MISC_EVCNT_ATTACH(rxq, qdrop, rxq, i, xname);
 #endif /* WM_EVENT_COUNTERS */
 		rx_done++;
+	}
 	if (error)
 		goto fail_2;
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		char rndname[16];
 		snprintf(rndname, sizeof(rndname), "%sTXRX%d",
 		    device_xname(sc->sc_dev), i);
 		rnd_attach_source(&sc->sc_queue[i].rnd_source, rndname,
 @@ -8107,26 +8131,28 @@ wm_free_txrx_queues(struct wm_softc *sc)
 	int i;
 	for (i = 0; i < sc->sc_nqueues; i++)
 		rnd_detach_source(&sc->sc_queue[i].rnd_source);
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 #ifdef WM_EVENT_COUNTERS
 		WM_Q_EVCNT_DETACH(rxq, intr, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, defer, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, ipsum, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, tusum, rxq, i);
 		if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
 			WM_Q_EVCNT_DETACH(rxq, qdrop, rxq, i);
 #endif /* WM_EVENT_COUNTERS */
 		wm_free_rx_buffer(sc, rxq);
 		wm_free_rx_descs(sc, rxq);
 		if (rxq->rxq_lock)
 			mutex_obj_free(rxq->rxq_lock);
+	}
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		struct mbuf *m;
 #ifdef WM_EVENT_COUNTERS
 		int j;
 @@ -8296,37 +8322,47 @@ wm_init_rx_regs(struct wm_softc *sc, str
 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
 	} else {
 		int qid = wmq->wmq_id;
 		CSR_WRITE(sc, WMREG_RDBAH(qid), WM_CDRXADDR_HI(rxq, 0));
 		CSR_WRITE(sc, WMREG_RDBAL(qid), WM_CDRXADDR_LO(rxq, 0));
 		CSR_WRITE(sc, WMREG_RDLEN(qid),
 		    rxq->rxq_descsize * rxq->rxq_ndesc);
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 			uint32_t srrctl;
 			if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
 				panic("%s: MCLBYTES %d unsupported for 82575 "
 				    "or higher\n", __func__, MCLBYTES);
 			/*
 			 * Currently, support SRRCTL_DESCTYPE_ADV_ONEBUF
 			 * only.
 			 */
-			CSR_WRITE(sc, WMREG_SRRCTL(qid),
+			srrctl = SRRCTL_DESCTYPE_ADV_ONEBUF
-			    SRRCTL_DESCTYPE_ADV_ONEBUF
+			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT);
-			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
+			/*
 			 * Drop frames if the RX descriptor ring has no room.
 			 * This is enabled only on multiqueue system to avoid
 			 * bad influence to other queues.
 			 */
 			if (sc->sc_nqueues > 1)
 				srrctl |= SRRCTL_DROP_EN;
 			CSR_WRITE(sc, WMREG_SRRCTL(qid), srrctl);
 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_QUEUE_ENABLE
 			    | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
 			    | RXDCTL_WTHRESH(1));
 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
 		} else {
 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
 			/* XXX should update with AIM? */
 			CSR_WRITE(sc, WMREG_RDTR,
 			    (wmq->wmq_itr / 4) | RDTR_FPD);
 			/* MUST be same */
 			CSR_WRITE(sc, WMREG_RADV, wmq->wmq_itr / 4);
 @@ -10933,29 +10969,29 @@ wm_linkintr_msix(void *arg)
 	if (sc->sc_core_stopping)
 		goto out;
 	if ((reg & ICR_LSC) != 0) {
 		WM_EVCNT_INCR(&sc->sc_ev_linkintr);
 		wm_linkintr(sc, ICR_LSC);
+	}
 	if ((reg & ICR_GPI(0)) != 0)
 		device_printf(sc->sc_dev, "got module interrupt\n");
 	/*
 	 * XXX 82574 MSI-X mode workaround
+	 *
-	 * 82574 MSI-X mode causes receive overrun(RXO) interrupt as ICR_OTHER
+	 * 82574 MSI-X mode causes a receive overrun(RXO) interrupt as an
-	 * MSI-X vector, furthermore it does not cause neigher ICR_RXQ(0) nor
+	 * ICR_OTHER MSI-X vector; furthermore it causes neither ICR_RXQ(0)
-	 * ICR_RXQ(1) vector. So, we generate ICR_RXQ(0) and ICR_RXQ(1)
+	 * nor ICR_RXQ(1) vectors. So, we generate ICR_RXQ(0) and ICR_RXQ(1)
 	 * interrupts by writing WMREG_ICS to process receive packets.
 	 */
 	if (sc->sc_type == WM_T_82574 && ((reg & ICR_RXO) != 0)) {
 #if defined(WM_DEBUG)
 		log(LOG_WARNING, "%s: Receive overrun\n",
 		    device_xname(sc->sc_dev));
 #endif /* defined(WM_DEBUG) */
 		has_rxo = true;
 		/*
 		 * The RXO interrupt is very high rate when receive traffic is
 		 * high rate. We use polling mode for ICR_OTHER like Tx/Rx
 		 * interrupts. ICR_OTHER will be enabled at the end of
 @@ -14963,36 +14999,37 @@ printver:
 		    sc->sc_nvm_ver_minor);
 		if (have_build) {
 			sc->sc_nvm_ver_build = build;
 			aprint_verbose(".%d", build);
+		}
+	}
 	/* Assume the Option ROM area is at avove NVM_SIZE */
 	if ((sc->sc_nvm_wordsize > NVM_SIZE) && check_optionrom
 	    && (wm_nvm_read(sc, NVM_OFF_COMB_VER_PTR, 1, &off) == 0)) {
 		/* Option ROM Version */
 		if ((off != 0x0000) && (off != 0xffff)) {
 			int rv;
 			uint16_t oid0, oid1;
 			off += NVM_COMBO_VER_OFF;
-			rv = wm_nvm_read(sc, off + 1, 1, &uid1);
+			rv = wm_nvm_read(sc, off + 1, 1, &oid1);
-			rv |= wm_nvm_read(sc, off, 1, &uid0);
+			rv |= wm_nvm_read(sc, off, 1, &oid0);
-			if ((rv == 0) && (uid0 != 0) && (uid0 != 0xffff)
+			if ((rv == 0) && (oid0 != 0) && (oid0 != 0xffff)
-			    && (uid1 != 0) && (uid1 != 0xffff)) {
+			    && (oid1 != 0) && (oid1 != 0xffff)) {
 				/* 16bits */
-				major = uid0 >> 8;
+				major = oid0 >> 8;
-				build = (uid0 << 8) | (uid1 >> 8);
+				build = (oid0 << 8) | (oid1 >> 8);
-				patch = uid1 & 0x00ff;
+				patch = oid1 & 0x00ff;
 				aprint_verbose(", option ROM Version %d.%d.%d",
 				    major, build, patch);
+			}
+		}
+	}
 	if (have_uid && (wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0) == 0))
 		aprint_verbose(", Image Unique ID %08x",
 		    ((uint32_t)uid1 << 16) | uid0);
+}
 /*
  * wm_nvm_read:

 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_wmreg.h,v 1.98.6.18 2023/10/18 14:41:54 martin Exp $	*/
+/*	$NetBSD: if_wmreg.h,v 1.98.6.19 2024/02/29 10:46:28 martin Exp $	*/
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -847,26 +847,29 @@ struct livengood_tcpip_ctxdesc {
 	    (0x0c018 + ((x) * 0x40)))
 #define	WMREG_RXDCTL(x) \
 	((x) < 4 ? (0x02828 + ((x) * 0x100)) :	\
 	    (0x0c028 + ((x) * 0x40)))	/* Receive Descriptor Control */
 #define	RXDCTL_PTHRESH(x) ((x) << 0)	/* prefetch threshold */
 #define	RXDCTL_HTHRESH(x) ((x) << 8)	/* host threshold */
 #define	RXDCTL_WTHRESH(x) ((x) << 16)	/* write back threshold */
 #define	RXDCTL_GRAN	__BIT(24)	/* 0 = cacheline, 1 = descriptor */
 /* flags used starting with 82575 ... */
 #define	RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
 #define	RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
 #define	WMREG_RQDPC(x)	(((x) < 4) ? (0x2830 + (0x100 * (x))) :		\
 	    (0xc030 + (0x40 * (x)))) /* Receive Queue Drop Packet Count */
 #define	WMREG_OLD_RDTR1	0x0130	/* Receive Delay Timer (ring 1) */
 #define	WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */
 #define	WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */
 #define	WMREG_OLD_RDLEN1 0x0140	/* Receive Drscriptor Length (ring 1) */
 #define	WMREG_OLD_RDH1	0x0148
 #define	WMREG_OLD_RDT1	0x0150
 #define	WMREG_OLD_FCRTH 0x0160	/* Flow Control Rx Threshold Hi (OLD) */
 #define	WMREG_FCRTH	0x2168	/* Flow Control Rx Threhsold Hi */
 #define	FCRTH_DFLT	0x00008000
 #define	WMREG_OLD_FCRTL 0x0168	/* Flow Control Rx Threshold Lo (OLD) */
 #define	WMREG_FCRTL	0x2160	/* Flow Control Rx Threshold Lo */
 #define	FCRTL_DFLT	0x00004000