Now
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Trailing whitespace
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Improve the comment.
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Fix 32bit UVMHIST builds
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arm has been fixed
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arm longjmp: Restore stack first, then signal mask.
Otherwise, a pending signal may be delivered on the wrong stack when
we restore the signal mask.
While here:
- Move the botched sp and lr tests earlier.
PR lib/57946
Otherwise, a pending signal may be delivered on the wrong stack when
we restore the signal mask.
While here:
- Move the botched sp and lr tests earlier.
PR lib/57946
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Remove magic numbers. NFCI.
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makecontext: correct the type to setup register based arguments.
Use __greg_t rather than int for register based arguments. This fixes
various atf tests.
Use __greg_t rather than int for register based arguments. This fixes
various atf tests.
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Fix the __greg_t typedef for riscv32
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Whitespace
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Small simplification. NFCI.
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Use the _X_FOO register macros instead of magic numbers.
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KNF
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More debug.
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Remove references to RISC-V.
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src/sys/arch/riscv/include/locore.h@1.13
/
diff
/
nxr@1.13
src/sys/arch/riscv/riscv/cpu_switch.S@1.6 / diff / nxr@1.6
src/sys/arch/riscv/riscv/trap.c@1.26 / diff / nxr@1.26
src/sys/arch/riscv/riscv/cpu_switch.S@1.6 / diff / nxr@1.6
src/sys/arch/riscv/riscv/trap.c@1.26 / diff / nxr@1.26
risc-v: fix the error code when uvm_fault fails with cpu_set_onfault
Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.
Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.
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Whitespace
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Whitespace
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Ensure a user specified DBG isn't used for xxboot.
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Whitespace
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Fix some usb_syncmem calls and add some missing ones.
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Whitespace.
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src/lib/libc/arch/hppa/gen/__setjmp14.S@1.10
/
diff
/
nxr@1.10
src/lib/libc/arch/hppa/genassym.cf@1.5 / diff / nxr@1.5
src/lib/libc/arch/hppa/genassym.cf@1.5 / diff / nxr@1.5
Remove some magic numbers by using genassym.cf
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Fix types in pmap_page_clear_attributes so that the top bits of
the u_long mdpg_attrs aren't dropped giving atomic_cas_ulong no
chance of completing if any of the top bits is set.
Update pmap_page_set_attributes for consistency.
An ATF test run completed for me with this fix.
port-riscv/58006: ATF tests no longer complete on riscv-riscv64
the u_long mdpg_attrs aren't dropped giving atomic_cas_ulong no
chance of completing if any of the top bits is set.
Update pmap_page_set_attributes for consistency.
An ATF test run completed for me with this fix.
port-riscv/58006: ATF tests no longer complete on riscv-riscv64
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Re-enable HEARTBEAT
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Fix alignment of ddb 'ps/[lw]' output. LID matches PID and has more digits.
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src/sys/arch/aarch64/aarch64/cpu_machdep.c@1.15
/
diff
/
nxr@1.15
src/sys/arch/aarch64/aarch64/sig_machdep.c@1.9 / diff / nxr@1.9
src/sys/arch/aarch64/aarch64/sig_machdep.c@1.9 / diff / nxr@1.9
kern/58149: aarch64: Cannot return from a signal handler if SP was misaligned when the signal arrived
Apply the kernel diff from the PR
1. sendsig_siginfo() previously assumed that user SP was always aligned to
16 bytes and could call signal handlers with SP misaligned. This is a
wrong assumption because aarch64 demands that SP is aligned *only while*
it's being used to access memory. Now it properly aligns it before
pusing anything on the stack.
2. cpu_mcontext_validate() used to check if _REG_SP was aligned and
considered the ucontext invalid otherwise. This meant if a signal was
sent to a process whose SP was misaligned, the signal handler would fail
to return because the ucontext passed from the kernel was an invalid
one. Now setcontext(2) doesn't complain about misaligned SP.
Apply the kernel diff from the PR
1. sendsig_siginfo() previously assumed that user SP was always aligned to
16 bytes and could call signal handlers with SP misaligned. This is a
wrong assumption because aarch64 demands that SP is aligned *only while*
it's being used to access memory. Now it properly aligns it before
pusing anything on the stack.
2. cpu_mcontext_validate() used to check if _REG_SP was aligned and
considered the ucontext invalid otherwise. This meant if a signal was
sent to a process whose SP was misaligned, the signal handler would fail
to return because the ucontext passed from the kernel was an invalid
one. Now setcontext(2) doesn't complain about misaligned SP.
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Trailing whitespace.
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port-arm/58135: reproducible pmap KASSERT failure for armv7 with NFS root
Don't unconditionally set XN in pmap_clearbit - only set it if a mapping
exists VM_PROT_EXEC is being cleared.
I've simplified the #ifdefs in the patch from the PR.
Don't unconditionally set XN in pmap_clearbit - only set it if a mapping
exists VM_PROT_EXEC is being cleared.
I've simplified the #ifdefs in the patch from the PR.
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Restore a space I accidentally removed from a copyright with
$NetBSD: pmap.c,v 1.396 2020/03/13 16:14:18 skrll Exp $
$NetBSD: pmap.c,v 1.396 2020/03/13 16:14:18 skrll Exp $
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Attach qemufwcfg
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Add RISC-V support
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Fix riscv32 build
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src/sys/arch/riscv/conf/files.riscv@1.15
/
diff
/
nxr@1.15
src/sys/arch/riscv/include/types.h@1.17 / diff / nxr@1.17
src/sys/arch/riscv/riscv/copy.S@1.1 / diff / nxr@1.1
src/sys/arch/riscv/riscv/genassym.cf@1.16 / diff / nxr@1.16
src/sys/arch/riscv/include/types.h@1.17 / diff / nxr@1.17
src/sys/arch/riscv/riscv/copy.S@1.1 / diff / nxr@1.1
src/sys/arch/riscv/riscv/genassym.cf@1.16 / diff / nxr@1.16
Provide and use _ucas_{32,64} implementations
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Return the correct error from {fetch,store}_user_data and fix
futex_wake_op_op: [0.273033s] Failed: /usr/src/tests/lib/libc/sys/t_futex_ops.c:942: Expected errno 14, got 1, in __futex(&futex_word, FUTEX_WAKE_OP | flags, 0, NULL, NULL, 0, op) == -1
futex_wake_op_op: [0.273033s] Failed: /usr/src/tests/lib/libc/sys/t_futex_ops.c:942: Expected errno 14, got 1, in __futex(&futex_word, FUTEX_WAKE_OP | flags, 0, NULL, NULL, 0, op) == -1
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src/sys/arch/riscv/dev/plic.c@1.5
/
diff
/
nxr@1.5
src/sys/arch/riscv/dev/plic_fdt.c@1.6 / diff / nxr@1.6
src/sys/arch/riscv/dev/plic_fdt.c@1.6 / diff / nxr@1.6
Pretty print plic attachment
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Add ld[4-7] and scsibus[123]
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Default pmap_stealdebug to false
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Remove #ifdef DIAGNOSTIC by using __diagused. NFCI.
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Change the PMAP_STEAL_MEMORY debug output from aprint_debug.
The new printfs are conditional on pmap_stealdebug and the DEBUG compile
option. The former defaults to true, but can be changed at a boot -d ddb
prompt.
The new printfs are conditional on pmap_stealdebug and the DEBUG compile
option. The former defaults to true, but can be changed at a boot -d ddb
prompt.
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Reorder the bus_dmamap_sync sync operations
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD to
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE
for consistency.
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD to
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE
for consistency.
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More KNF (whitespace around binary operators)
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Use __BIT.
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Enforce the device 32 bit DMA limitation via bus_dmatag_subregion if bus
can address more than 4GB.
can address more than 4GB.
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KNF - spaces around binary operators.
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Remove unused "SHIFT" defines. The "MASK" versions exist.
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Warn about building a kernel with the wrong toolchain.
Idea from mrg@
Idea from mrg@
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Add ARM_HAS_VBAR
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Steal the sync operation descriptions from FreeBSD and improve other
wording in this area.
Inspired by jmcneill@
wording in this area.
Inspired by jmcneill@
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src/sys/arch/arm/broadcom/bcm53xx_board.c@1.27
/
diff
/
nxr@1.27
src/sys/arch/arm/broadcom/files.bcm53xx@1.6 / diff / nxr@1.6
src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c@1.29 / diff / nxr@1.29
src/sys/arch/evbarm/conf/BCM5301X@1.40 / diff / nxr@1.40
src/sys/arch/evbarm/conf/BCM56340@1.23 / diff / nxr@1.23
src/sys/arch/arm/broadcom/files.bcm53xx@1.6 / diff / nxr@1.6
src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c@1.29 / diff / nxr@1.29
src/sys/arch/evbarm/conf/BCM5301X@1.40 / diff / nxr@1.40
src/sys/arch/evbarm/conf/BCM56340@1.23 / diff / nxr@1.23
Retire BCM53XX_CONSOLE_EARLY in favour of EARLYCONS
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Test sc->sc_soft_ih (not sc->sc_ih) to see if the soft interrupt got
established correctly.
From Mori Hiroki.
Fix some error recovery while I'm here.
established correctly.
From Mori Hiroki.
Fix some error recovery while I'm here.
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src/sys/arch/arm/broadcom/bcm2835_bsc.c@1.16
/
diff
/
nxr@1.16
src/sys/arch/arm/broadcom/bcm2835_vcaudio.c@1.20 / diff / nxr@1.20
src/sys/arch/arm/broadcom/bcm2838_pcie.c@1.7 / diff / nxr@1.7
src/sys/arch/arm/broadcom/bcm2835_vcaudio.c@1.20 / diff / nxr@1.20
src/sys/arch/arm/broadcom/bcm2838_pcie.c@1.7 / diff / nxr@1.7
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src/sys/arch/arm/broadcom/bcm53xx_board.c@1.26
/
diff
/
nxr@1.26
src/sys/arch/arm/broadcom/bcm53xx_cca.c@1.6 / diff / nxr@1.6
src/sys/arch/arm/broadcom/bcm53xx_idm.c@1.4 / diff / nxr@1.4
src/sys/arch/arm/broadcom/bcm53xx_pax.c@1.24 / diff / nxr@1.24
src/sys/arch/arm/broadcom/bcm53xx_reg.h@1.20 / diff / nxr@1.20
src/sys/arch/arm/broadcom/bcm53xx_cca.c@1.6 / diff / nxr@1.6
src/sys/arch/arm/broadcom/bcm53xx_idm.c@1.4 / diff / nxr@1.4
src/sys/arch/arm/broadcom/bcm53xx_pax.c@1.24 / diff / nxr@1.24
src/sys/arch/arm/broadcom/bcm53xx_reg.h@1.20 / diff / nxr@1.20
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src/sys/arch/arm/broadcom/bcm53xx_eth.c@1.43
/
diff
/
nxr@1.43
src/sys/arch/arm/broadcom/bcm53xx_pax.c@1.23 / diff / nxr@1.23
src/sys/arch/arm/broadcom/bcm53xx_pax.c@1.23 / diff / nxr@1.23
Fix non-DIAGNOSTIC build
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src/sys/arch/arm/broadcom/bcm53xx_board.c@1.25.30.1
/
diff
/
nxr@1.25.30.1
src/sys/arch/arm/broadcom/bcm53xx_cca.c@1.5.4.1 / diff / nxr@1.5.4.1
src/sys/arch/arm/broadcom/bcm53xx_idm.c@1.3.70.1 / diff / nxr@1.3.70.1
src/sys/arch/arm/broadcom/bcm53xx_pax.c@1.22.6.1 / diff / nxr@1.22.6.1
src/sys/arch/arm/broadcom/bcm53xx_reg.h@1.19.4.1 / diff / nxr@1.19.4.1
src/sys/arch/arm/broadcom/bcm53xx_cca.c@1.5.4.1 / diff / nxr@1.5.4.1
src/sys/arch/arm/broadcom/bcm53xx_idm.c@1.3.70.1 / diff / nxr@1.3.70.1
src/sys/arch/arm/broadcom/bcm53xx_pax.c@1.22.6.1 / diff / nxr@1.22.6.1
src/sys/arch/arm/broadcom/bcm53xx_reg.h@1.19.4.1 / diff / nxr@1.19.4.1
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Define KERNEL_VOFFSET_RUNTIME=1 to fix build of BCM5301X and BCM56340
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Fix spello in debug output
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Fix a comment. arm32 stopped using 8K pages a long time ago.
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Turn off HEARTBEAT
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Fix an error message by removing an extra 'x'
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Restrict dwcmmc to 32bit DMA (<4GB) regardless of attachment
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Fix a typo in a comment
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Trailing whitespace
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Trailing whitespace.
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Attach ld at sdmmc
The SD card on my Beagle-V now works. Thanks jmcneill!
The SD card on my Beagle-V now works. Thanks jmcneill!
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Limit DMA to below 4GB - the supported controllers are limited this
way.
Thanks to jmcneill for a version of this patch.
way.
Thanks to jmcneill for a version of this patch.
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spaces to tabs
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Define _RISCV_NEED_BUS_DMA_BOUNCE.
Pointed out as being needed by jmcneill. Thanks!
Pointed out as being needed by jmcneill. Thanks!
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Some fixes from Roland Illig
- fix a locking bug
- '\n' at the end of error messages
- fix a locking bug
- '\n' at the end of error messages
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src/sys/arch/riscv/conf/GENERIC64@1.8
/
diff
/
nxr@1.8
src/sys/arch/riscv/starfive/files.starfive@1.3 / diff / nxr@1.3
src/sys/arch/riscv/starfive/jh7100_pinctrl.c@1.1 / diff / nxr@1.1
src/sys/arch/riscv/starfive/files.starfive@1.3 / diff / nxr@1.3
src/sys/arch/riscv/starfive/jh7100_pinctrl.c@1.1 / diff / nxr@1.1
risc-v: add a driver the JH7100 pin controller
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Use <space><tab> consistently
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Trailing whitespace
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Trailing whitespace.
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Fix column alignment in ps/w output
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Don't duplicate PIM_CPU_BITS in one printf.
PIM_CPU_HPMC_BITS already includes PIM_CPU_HPMC_BITS
PIM_CPU_HPMC_BITS already includes PIM_CPU_HPMC_BITS
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Fix one by one bugs I committed back in 2009. Spotted by rillig@.
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Make this compile without MULTIPROCESSOR
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Remove an empty line
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spaces -> tab
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Create some more nodes.
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src/distrib/sets/lists/base/md.riscv@1.1
/
diff
/
nxr@1.1
src/external/broadcom/bwfm/Makefile@1.10 / diff / nxr@1.10
src/share/mk/bsd.own.mk@1.1363 / diff / nxr@1.1363
src/external/broadcom/bwfm/Makefile@1.10 / diff / nxr@1.10
src/share/mk/bsd.own.mk@1.1363 / diff / nxr@1.1363
risc-v: Add bwfm(4) firmware files to release image
Create the correct link for beagle,beaglev-starlight-jh7100-r0.txt NVRAM
config file.
Create the correct link for beagle,beaglev-starlight-jh7100-r0.txt NVRAM
config file.
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Add bwfm* at sdmmc? for the Broadcom BCM43xxx WiFi Interface
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Add DesignWare SD/MMC attachment.
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Use fdt_cpu_rootconf
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src/sys/arch/evbarm/fdt/fdt_machdep.c@1.107
/
diff
/
nxr@1.107
src/sys/dev/fdt/fdt_boot.c@1.5 / diff / nxr@1.5
src/sys/dev/fdt/fdt_boot.h@1.4 / diff / nxr@1.4
src/sys/dev/fdt/fdt_boot.c@1.5 / diff / nxr@1.5
src/sys/dev/fdt/fdt_boot.h@1.4 / diff / nxr@1.4
Make fdt_cpu_rootconf available for other machines/platforms.
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src/sys/arch/riscv/conf/GENERIC64@1.4
/
diff
/
nxr@1.4
src/sys/arch/riscv/starfive/files.starfive@1.2 / diff / nxr@1.2
src/sys/arch/riscv/starfive/jh71x0_usb.c@1.1 / diff / nxr@1.1
src/sys/dev/fdt/cdns3_fdt.c@1.1 / diff / nxr@1.1
src/sys/dev/fdt/files.fdt@1.72 / diff / nxr@1.72
src/sys/arch/riscv/starfive/files.starfive@1.2 / diff / nxr@1.2
src/sys/arch/riscv/starfive/jh71x0_usb.c@1.1 / diff / nxr@1.1
src/sys/dev/fdt/cdns3_fdt.c@1.1 / diff / nxr@1.1
src/sys/dev/fdt/files.fdt@1.72 / diff / nxr@1.72
risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
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src/sys/arch/riscv/riscv/clock_machdep.c@1.7
/
diff
/
nxr@1.7
src/sys/arch/riscv/riscv/riscv_machdep.c@1.36 / diff / nxr@1.36
src/sys/arch/riscv/riscv/riscv_machdep.c@1.36 / diff / nxr@1.36
Provide a working delay(9)
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Fix types of constants
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Implement jh7100_clkc_fracdiv_get_rate
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src/sys/arch/riscv/conf/GENERIC64@1.3
/
diff
/
nxr@1.3
src/sys/arch/riscv/conf/files.generic64@1.2 / diff / nxr@1.2
src/sys/arch/riscv/starfive/files.starfive@1.1 / diff / nxr@1.1
src/sys/arch/riscv/starfive/jh7100_clkc.c@1.1 / diff / nxr@1.1
src/sys/arch/riscv/starfive/jh7100_clkc.h@1.1 / diff / nxr@1.1
src/sys/arch/riscv/conf/files.generic64@1.2 / diff / nxr@1.2
src/sys/arch/riscv/starfive/files.starfive@1.1 / diff / nxr@1.1
src/sys/arch/riscv/starfive/jh7100_clkc.c@1.1 / diff / nxr@1.1
src/sys/arch/riscv/starfive/jh7100_clkc.h@1.1 / diff / nxr@1.1
risc-v: add a StarTech JH7100 SoC clock driver
The JH7100 is seen in the Beagle-V board.
The JH7100 is seen in the Beagle-V board.
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The dr_node should be a property of usb_cdns3 and not usb3 for jh7100.
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src/distrib/sets/lists/dtb/ad.riscv32@1.2
/
diff
/
nxr@1.2
src/distrib/sets/lists/dtb/ad.riscv64@1.2 / diff / nxr@1.2
src/sys/dtb/riscv/Makefile@1.2 / diff / nxr@1.2
src/sys/dtb/riscv/starfive/Makefile@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/Makefile@1.2 / diff / nxr@1.2
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/Makefile@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-common.dtsi@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100.dtsi@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110.dtsi@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/starfive,jh7110-crg.h@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/starfive-jh7100-audio.h@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/starfive-jh7100.h@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h@1.1 / diff / nxr@1.1
:
(more 6 files)
src/distrib/sets/lists/dtb/ad.riscv64@1.2 / diff / nxr@1.2
src/sys/dtb/riscv/Makefile@1.2 / diff / nxr@1.2
src/sys/dtb/riscv/starfive/Makefile@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/Makefile@1.2 / diff / nxr@1.2
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/Makefile@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-common.dtsi@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7100.dtsi@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/jh7110.dtsi@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/starfive,jh7110-crg.h@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/starfive-jh7100-audio.h@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/starfive-jh7100.h@1.1 / diff / nxr@1.1
src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h@1.1 / diff / nxr@1.1
:
(more 6 files)
Import RISC-V starfive DTS from https://github.com/starfive-tech/linux.git"
The files are taken from the visionfive branch with latest DTS related commit
commit 9b5f280fa413ee76fac20cd575075fc53468d527
Author: Emil Renner Berthing <kernel@esmil.dk>
Date: Sun Oct 31 17:15:58 2021 +0100
riscv: dts: Add full JH7100, Starlight and VisionFive support
The files are taken from the visionfive branch with latest DTS related commit
commit 9b5f280fa413ee76fac20cd575075fc53468d527
Author: Emil Renner Berthing <kernel@esmil.dk>
Date: Sun Oct 31 17:15:58 2021 +0100
riscv: dts: Add full JH7100, Starlight and VisionFive support
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risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs.
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src/sys/arch/riscv/conf/GENERIC64@1.2
/
diff
/
nxr@1.2
src/sys/arch/riscv/sifive/files.sifive@1.3 / diff / nxr@1.3
src/sys/arch/riscv/sifive/fu540_ccache.c@1.1 / diff / nxr@1.1
src/sys/arch/riscv/sifive/files.sifive@1.3 / diff / nxr@1.3
src/sys/arch/riscv/sifive/fu540_ccache.c@1.1 / diff / nxr@1.1
risc-v: add a SiFive FU[57]40/ L2 Cache controller driver
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Attach generic system controllers
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Group pass 1 attachments
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Cache the result from fdtbus_get_data() in fdt_memory_remove_reserved
NFCI.
NFCI.
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src/sys/arch/riscv/include/pmap.h@1.23
/
diff
/
nxr@1.23
src/sys/arch/riscv/riscv/pmap_machdep.c@1.20 / diff / nxr@1.20
src/sys/arch/riscv/riscv/pmap_machdep.c@1.20 / diff / nxr@1.20
risc-v: probe the number of supported ASIDs
Flush the entire TLB if no ASIDs are supported on pmap_activate.
Flush the entire TLB if no ASIDs are supported on pmap_activate.
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Appease KASSERTs for zero ASID CPUs (I mean harts)
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src/sys/arch/riscv/dev/plic_fdt.c@1.4
/
diff
/
nxr@1.4
src/sys/arch/riscv/fdt/cpu_fdt.c@1.4 / diff / nxr@1.4
src/sys/arch/riscv/fdt/riscv_fdtvar.h@1.2 / diff / nxr@1.2
src/sys/arch/riscv/fdt/cpu_fdt.c@1.4 / diff / nxr@1.4
src/sys/arch/riscv/fdt/riscv_fdtvar.h@1.2 / diff / nxr@1.2
Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
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dwcmmc_fdt_bus_clock: fix an aprint_debug_dev frequency units botch.
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src/external/broadcom/rpi-firmware/dist/LICENCE.broadcom@1.3
/
diff
/
nxr@1.3
src/external/broadcom/rpi-firmware/dist/bootcode.bin@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/fixup.dat@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/fixup4.dat@1.2 / diff / nxr@1.2
src/external/broadcom/rpi-firmware/dist/fixup4cd.dat@1.2 / diff / nxr@1.2
src/external/broadcom/rpi-firmware/dist/fixup_cd.dat@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/start.elf@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/start4.elf@1.2 / diff / nxr@1.2
src/external/broadcom/rpi-firmware/dist/start4cd.elf@1.2 / diff / nxr@1.2
src/external/broadcom/rpi-firmware/dist/start_cd.elf@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/bootcode.bin@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/fixup.dat@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/fixup4.dat@1.2 / diff / nxr@1.2
src/external/broadcom/rpi-firmware/dist/fixup4cd.dat@1.2 / diff / nxr@1.2
src/external/broadcom/rpi-firmware/dist/fixup_cd.dat@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/start.elf@1.13 / diff / nxr@1.13
src/external/broadcom/rpi-firmware/dist/start4.elf@1.2 / diff / nxr@1.2
src/external/broadcom/rpi-firmware/dist/start4cd.elf@1.2 / diff / nxr@1.2
src/external/broadcom/rpi-firmware/dist/start_cd.elf@1.13 / diff / nxr@1.13
Update RaspberryPI firmware
Update the RaspberryPI firmware to the version from
https://github.com/raspberrypi/rpi-firmware
commit fdb9eafae4b83e553593937eae8e77b0193903c3
Author: Dom Cobley <popcornmix@gmail.com>
Date: Tue Oct 17 15:59:45 2023 +0100
kernel: Bump to 6.1.58
...
firmware: config: Add [pi5] to config.txt on 2711 and earlier platforms
Update the RaspberryPI firmware to the version from
https://github.com/raspberrypi/rpi-firmware
commit fdb9eafae4b83e553593937eae8e77b0193903c3
Author: Dom Cobley <popcornmix@gmail.com>
Date: Tue Oct 17 15:59:45 2023 +0100
kernel: Bump to 6.1.58
...
firmware: config: Add [pi5] to config.txt on 2711 and earlier platforms
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G/C ununsed and incorrect SIE_IM
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src/sys/arch/riscv/fdt/intc_fdt.c@1.3
/
diff
/
nxr@1.3
src/sys/arch/riscv/include/cpu.h@1.15 / diff / nxr@1.15
src/sys/arch/riscv/include/cpu.h@1.15 / diff / nxr@1.15
Count interrupts across harts and their local interrupt controllers
correctly.
correctly.
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Deliver plic interrupts to the cpu^Whart establishing the interrupt
handler. At least this is known to be a valid hart, but it might share
some interrupts around too.
handler. At least this is known to be a valid hart, but it might share
some interrupts around too.
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src/sys/arch/arm/rockchip/rk_eqos.c@1.2
/
diff
/
nxr@1.2
src/sys/dev/acpi/eqos_acpi.c@1.2 / diff / nxr@1.2
src/sys/dev/ic/dwc_eqos.c@1.35 / diff / nxr@1.35
src/sys/dev/acpi/eqos_acpi.c@1.2 / diff / nxr@1.2
src/sys/dev/ic/dwc_eqos.c@1.35 / diff / nxr@1.35
eqos(4): MP improvements
Remove the non-MP-safe scaffolding and pass MP safe flags for callout
and interrupt handlers.
Where we had #ifndef EQOS_MPSAFE splnet(), we also had EQOS_LOCK,
which implies splnet, so just remove the conditional splnet.
Remove the non-MP-safe scaffolding and pass MP safe flags for callout
and interrupt handlers.
Where we had #ifndef EQOS_MPSAFE splnet(), we also had EQOS_LOCK,
which implies splnet, so just remove the conditional splnet.
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src/sys/arch/riscv/riscv/db_interface.c@1.5
/
diff
/
nxr@1.5
src/sys/arch/riscv/riscv/riscv_machdep.c@1.35 / diff / nxr@1.35
src/sys/arch/riscv/riscv/riscv_machdep.c@1.35 / diff / nxr@1.35
Minor stylistic changes. NFCI.
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G/C sc_task and #include "opt_net_mpsafe.h"
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src/sys/dev/hyperv/if_hvn.c@1.26
/
diff
/
nxr@1.26
src/sys/dev/ic/dwc_gmac.c@1.80 / diff / nxr@1.80
src/sys/dev/pci/if_ena.c@1.41 / diff / nxr@1.41
src/sys/dev/pci/if_ixl.c@1.96 / diff / nxr@1.96
src/sys/dev/pci/igc/if_igc.c@1.9 / diff / nxr@1.9
src/sys/dev/scsipi/if_dse.c@1.4 / diff / nxr@1.4
src/sys/dev/scsipi/if_se.c@1.119 / diff / nxr@1.119
src/sys/dev/ic/dwc_gmac.c@1.80 / diff / nxr@1.80
src/sys/dev/pci/if_ena.c@1.41 / diff / nxr@1.41
src/sys/dev/pci/if_ixl.c@1.96 / diff / nxr@1.96
src/sys/dev/pci/igc/if_igc.c@1.9 / diff / nxr@1.9
src/sys/dev/scsipi/if_dse.c@1.4 / diff / nxr@1.4
src/sys/dev/scsipi/if_se.c@1.119 / diff / nxr@1.119
Remove unnecssary #include
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Remove unnecessary #include
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Use un_flags as pointed out by mrg@ thanks.
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Add support for AX88179A. From sc.dying on current-users.
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Free memory on failure
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Fix cross compiling by using snprintf instead of strlcpy
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Define __HAVE_ATOMIC_CAS_64_UP and provide __sync_val_compare_and_swap_8
The new santizer code in gcc12 needs this.
The new santizer code in gcc12 needs this.
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<spaces> -> <tabs>
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Update hppa status
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src/sys/arch/arm/arm32/pmap.c@1.440
/
diff
/
nxr@1.440
src/sys/arch/arm/include/arm32/pmap.h@1.177 / diff / nxr@1.177
src/sys/arch/evbarm/adi_brh/brh_machdep.c@1.53 / diff / nxr@1.53
src/sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c@1.41 / diff / nxr@1.41
src/sys/arch/evbarm/gumstix/gumstix_machdep.c@1.75 / diff / nxr@1.75
src/sys/arch/evbarm/hdl_g/hdlg_machdep.c@1.35 / diff / nxr@1.35
src/sys/arch/evbarm/iq80310/iq80310_machdep.c@1.96 / diff / nxr@1.96
src/sys/arch/evbarm/iq80321/iq80321_machdep.c@1.66 / diff / nxr@1.66
src/sys/arch/evbarm/ixdp425/ixdp425_machdep.c@1.47 / diff / nxr@1.47
src/sys/arch/evbarm/iyonix/iyonix_machdep.c@1.5 / diff / nxr@1.5
src/sys/arch/evbarm/lubbock/lubbock_machdep.c@1.45 / diff / nxr@1.45
src/sys/arch/evbarm/npwr_fc/npwr_fc_machdep.c@1.30 / diff / nxr@1.30
src/sys/arch/evbarm/nslu2/nslu2_machdep.c@1.41 / diff / nxr@1.41
src/sys/arch/evbarm/viper/viper_machdep.c@1.34 / diff / nxr@1.34
src/sys/arch/hpcarm/hpcarm/pxa2x0_hpc_machdep.c@1.33 / diff / nxr@1.33
src/sys/arch/iyonix/iyonix/iyonix_machdep.c@1.34 / diff / nxr@1.34
src/sys/arch/zaurus/zaurus/machdep.c@1.52 / diff / nxr@1.52
src/sys/arch/arm/include/arm32/pmap.h@1.177 / diff / nxr@1.177
src/sys/arch/evbarm/adi_brh/brh_machdep.c@1.53 / diff / nxr@1.53
src/sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c@1.41 / diff / nxr@1.41
src/sys/arch/evbarm/gumstix/gumstix_machdep.c@1.75 / diff / nxr@1.75
src/sys/arch/evbarm/hdl_g/hdlg_machdep.c@1.35 / diff / nxr@1.35
src/sys/arch/evbarm/iq80310/iq80310_machdep.c@1.96 / diff / nxr@1.96
src/sys/arch/evbarm/iq80321/iq80321_machdep.c@1.66 / diff / nxr@1.66
src/sys/arch/evbarm/ixdp425/ixdp425_machdep.c@1.47 / diff / nxr@1.47
src/sys/arch/evbarm/iyonix/iyonix_machdep.c@1.5 / diff / nxr@1.5
src/sys/arch/evbarm/lubbock/lubbock_machdep.c@1.45 / diff / nxr@1.45
src/sys/arch/evbarm/npwr_fc/npwr_fc_machdep.c@1.30 / diff / nxr@1.30
src/sys/arch/evbarm/nslu2/nslu2_machdep.c@1.41 / diff / nxr@1.41
src/sys/arch/evbarm/viper/viper_machdep.c@1.34 / diff / nxr@1.34
src/sys/arch/hpcarm/hpcarm/pxa2x0_hpc_machdep.c@1.33 / diff / nxr@1.33
src/sys/arch/iyonix/iyonix/iyonix_machdep.c@1.34 / diff / nxr@1.34
src/sys/arch/zaurus/zaurus/machdep.c@1.52 / diff / nxr@1.52
Fix non-DIAGNOSTIC builds
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src/lib/libc/arch/ia64/gen/setjmp.S@1.3
/
diff
/
nxr@1.3
src/lib/libc/arch/or1k/gen/__setjmp14.S@1.2 / diff / nxr@1.2
src/lib/libc/arch/powerpc/gen/__setjmp14.S@1.6 / diff / nxr@1.6
src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S@1.6 / diff / nxr@1.6
src/lib/libc/arch/powerpc64/gen/__setjmp14.S@1.5 / diff / nxr@1.5
src/lib/libc/arch/powerpc64/gen/__sigsetjmp14.S@1.4 / diff / nxr@1.4
src/lib/libc/arch/riscv/gen/__setjmp14.S@1.5 / diff / nxr@1.5
src/lib/libc/arch/sh3/gen/setjmp.S@1.11 / diff / nxr@1.11
src/lib/libc/arch/sh3/gen/sigsetjmp.S@1.10 / diff / nxr@1.10
src/lib/libc/arch/sparc/gen/setjmp.S@1.14 / diff / nxr@1.14
src/lib/libc/arch/sparc64/gen/setjmp.S@1.12 / diff / nxr@1.12
src/lib/libc/arch/or1k/gen/__setjmp14.S@1.2 / diff / nxr@1.2
src/lib/libc/arch/powerpc/gen/__setjmp14.S@1.6 / diff / nxr@1.6
src/lib/libc/arch/powerpc/gen/__sigsetjmp14.S@1.6 / diff / nxr@1.6
src/lib/libc/arch/powerpc64/gen/__setjmp14.S@1.5 / diff / nxr@1.5
src/lib/libc/arch/powerpc64/gen/__sigsetjmp14.S@1.4 / diff / nxr@1.4
src/lib/libc/arch/riscv/gen/__setjmp14.S@1.5 / diff / nxr@1.5
src/lib/libc/arch/sh3/gen/setjmp.S@1.11 / diff / nxr@1.11
src/lib/libc/arch/sh3/gen/sigsetjmp.S@1.10 / diff / nxr@1.10
src/lib/libc/arch/sparc/gen/setjmp.S@1.14 / diff / nxr@1.14
src/lib/libc/arch/sparc64/gen/setjmp.S@1.12 / diff / nxr@1.12
Consistently pass 0 as first and ignored argument to sigprocmask in the
setjmp implementations.
NFCI.
setjmp implementations.
NFCI.
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src/sys/arch/alpha/alpha/vm_machdep.c@1.123
/
diff
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nxr@1.123
src/sys/arch/ia64/ia64/vm_machdep.c@1.20 / diff / nxr@1.20
src/sys/arch/sh3/sh3/vm_machdep.c@1.83 / diff / nxr@1.83
src/sys/arch/x86/x86/vm_machdep.c@1.46 / diff / nxr@1.46
src/sys/arch/ia64/ia64/vm_machdep.c@1.20 / diff / nxr@1.20
src/sys/arch/sh3/sh3/vm_machdep.c@1.83 / diff / nxr@1.83
src/sys/arch/x86/x86/vm_machdep.c@1.46 / diff / nxr@1.46
Convert the l2->l_md.md_astpending assignments into KASSERTs.
l_md is zeroised by lwp_create with
memset(&l2->l_startzero, 0, sizeof(*l2) -
offsetof(lwp_t, l_startzero));
l_md is zeroised by lwp_create with
memset(&l2->l_startzero, 0, sizeof(*l2) -
offsetof(lwp_t, l_startzero));
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src/sys/arch/ia64/include/asm.h@1.9
/
diff
/
nxr@1.9
src/sys/arch/ia64/include/bootinfo.h@1.3 / diff / nxr@1.3
src/sys/arch/ia64/include/cpu.h@1.22 / diff / nxr@1.22
src/sys/arch/ia64/include/db_machdep.h@1.5 / diff / nxr@1.5
src/sys/arch/ia64/include/ia64_cpu.h@1.4 / diff / nxr@1.4
src/sys/arch/ia64/include/int_limits.h@1.6 / diff / nxr@1.6
src/sys/arch/ia64/include/intrdefs.h@1.4 / diff / nxr@1.4
src/sys/arch/ia64/include/loadfile_machdep.h@1.4 / diff / nxr@1.4
src/sys/arch/ia64/include/lock.h@1.10 / diff / nxr@1.10
src/sys/arch/ia64/include/param.h@1.12 / diff / nxr@1.12
src/sys/arch/ia64/include/pmap.h@1.9 / diff / nxr@1.9
src/sys/arch/ia64/include/proc.h@1.11 / diff / nxr@1.11
src/sys/arch/ia64/include/setjmp.h@1.5 / diff / nxr@1.5
src/sys/arch/ia64/include/userret.h@1.2 / diff / nxr@1.2
src/sys/arch/ia64/include/vmparam.h@1.12 / diff / nxr@1.12
src/sys/arch/ia64/include/bootinfo.h@1.3 / diff / nxr@1.3
src/sys/arch/ia64/include/cpu.h@1.22 / diff / nxr@1.22
src/sys/arch/ia64/include/db_machdep.h@1.5 / diff / nxr@1.5
src/sys/arch/ia64/include/ia64_cpu.h@1.4 / diff / nxr@1.4
src/sys/arch/ia64/include/int_limits.h@1.6 / diff / nxr@1.6
src/sys/arch/ia64/include/intrdefs.h@1.4 / diff / nxr@1.4
src/sys/arch/ia64/include/loadfile_machdep.h@1.4 / diff / nxr@1.4
src/sys/arch/ia64/include/lock.h@1.10 / diff / nxr@1.10
src/sys/arch/ia64/include/param.h@1.12 / diff / nxr@1.12
src/sys/arch/ia64/include/pmap.h@1.9 / diff / nxr@1.9
src/sys/arch/ia64/include/proc.h@1.11 / diff / nxr@1.11
src/sys/arch/ia64/include/setjmp.h@1.5 / diff / nxr@1.5
src/sys/arch/ia64/include/userret.h@1.2 / diff / nxr@1.2
src/sys/arch/ia64/include/vmparam.h@1.12 / diff / nxr@1.12
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src/sys/arch/ia64/ia64/context.S@1.9
/
diff
/
nxr@1.9
src/sys/arch/ia64/ia64/db_trace.c@1.6 / diff / nxr@1.6
src/sys/arch/ia64/ia64/exception.S@1.7 / diff / nxr@1.7
src/sys/arch/ia64/ia64/genassym.cf@1.17 / diff / nxr@1.17
src/sys/arch/ia64/ia64/interrupt.c@1.12 / diff / nxr@1.12
src/sys/arch/ia64/ia64/locore.S@1.10 / diff / nxr@1.10
src/sys/arch/ia64/ia64/machdep.c@1.45 / diff / nxr@1.45
src/sys/arch/ia64/ia64/pal.S@1.2 / diff / nxr@1.2
src/sys/arch/ia64/ia64/pmap.c@1.43 / diff / nxr@1.43
src/sys/arch/ia64/ia64/process_machdep.c@1.7 / diff / nxr@1.7
src/sys/arch/ia64/ia64/setjmp.S@1.2 / diff / nxr@1.2
src/sys/arch/ia64/ia64/sys_machdep.c@1.7 / diff / nxr@1.7
src/sys/arch/ia64/ia64/syscall_stubs.S@1.7 / diff / nxr@1.7
src/sys/arch/ia64/ia64/vm_machdep.c@1.19 / diff / nxr@1.19
src/sys/arch/ia64/ia64/db_trace.c@1.6 / diff / nxr@1.6
src/sys/arch/ia64/ia64/exception.S@1.7 / diff / nxr@1.7
src/sys/arch/ia64/ia64/genassym.cf@1.17 / diff / nxr@1.17
src/sys/arch/ia64/ia64/interrupt.c@1.12 / diff / nxr@1.12
src/sys/arch/ia64/ia64/locore.S@1.10 / diff / nxr@1.10
src/sys/arch/ia64/ia64/machdep.c@1.45 / diff / nxr@1.45
src/sys/arch/ia64/ia64/pal.S@1.2 / diff / nxr@1.2
src/sys/arch/ia64/ia64/pmap.c@1.43 / diff / nxr@1.43
src/sys/arch/ia64/ia64/process_machdep.c@1.7 / diff / nxr@1.7
src/sys/arch/ia64/ia64/setjmp.S@1.2 / diff / nxr@1.2
src/sys/arch/ia64/ia64/sys_machdep.c@1.7 / diff / nxr@1.7
src/sys/arch/ia64/ia64/syscall_stubs.S@1.7 / diff / nxr@1.7
src/sys/arch/ia64/ia64/vm_machdep.c@1.19 / diff / nxr@1.19
Trailing whitespace.
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Not all RISC-V CPUs have ASIDs
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src/sys/uvm/pmap/pmap_tlb.c@1.61
/
diff
/
nxr@1.61
src/sys/uvm/pmap/pmap_tlb.h@1.17 / diff / nxr@1.17
src/sys/uvm/pmap/pmap_tlb.h@1.17 / diff / nxr@1.17
Support CPUs that might not have ASIDs in the common pmap.
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Apply the new diff from
kern/55273 urndis(4) error "could not find data bulk in/out" without CDC union descriptor
Fallback to the interface association descriptor if no CDC Union Descriptor is
found.
kern/55273 urndis(4) error "could not find data bulk in/out" without CDC union descriptor
Fallback to the interface association descriptor if no CDC Union Descriptor is
found.
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whitespace nit
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#define<space> -> #define<tab> for consistency
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#define<space> -> #define<tab> for consistency
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src/sys/arch/powerpc/include/ibm4xx/pmap.h@1.22
/
diff
/
nxr@1.22
src/sys/arch/powerpc/include/oea/pmap.h@1.38 / diff / nxr@1.38
src/sys/arch/powerpc/include/oea/pmap.h@1.38 / diff / nxr@1.38
Trailing whitespace.
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Add a bunch of system registers and their bit / bit field definitions.
Taken from ryo's nvmm branch with updates from me.
Taken from ryo's nvmm branch with updates from me.
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Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup
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src/sys/arch/riscv/conf/GENERIC.common@1.7
/
diff
/
nxr@1.7
src/sys/arch/riscv/conf/files.riscv@1.14 / diff / nxr@1.14
src/sys/arch/riscv/fdt/cpu_fdt.c@1.3 / diff / nxr@1.3
src/sys/arch/riscv/include/cpu.h@1.14 / diff / nxr@1.14
src/sys/arch/riscv/include/intr.h@1.5 / diff / nxr@1.5
src/sys/arch/riscv/include/pmap.h@1.21 / diff / nxr@1.21
src/sys/arch/riscv/riscv/cpu.c@1.5 / diff / nxr@1.5
src/sys/arch/riscv/riscv/cpu_subr.c@1.4 / diff / nxr@1.4
src/sys/arch/riscv/riscv/db_interface.c@1.4 / diff / nxr@1.4
src/sys/arch/riscv/riscv/ipifuncs.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/riscv/locore.S@1.43 / diff / nxr@1.43
src/sys/arch/riscv/riscv/pmap_machdep.c@1.19 / diff / nxr@1.19
src/sys/arch/riscv/riscv/riscv_machdep.c@1.34 / diff / nxr@1.34
src/sys/arch/riscv/riscv/riscv_tlb.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/conf/files.riscv@1.14 / diff / nxr@1.14
src/sys/arch/riscv/fdt/cpu_fdt.c@1.3 / diff / nxr@1.3
src/sys/arch/riscv/include/cpu.h@1.14 / diff / nxr@1.14
src/sys/arch/riscv/include/intr.h@1.5 / diff / nxr@1.5
src/sys/arch/riscv/include/pmap.h@1.21 / diff / nxr@1.21
src/sys/arch/riscv/riscv/cpu.c@1.5 / diff / nxr@1.5
src/sys/arch/riscv/riscv/cpu_subr.c@1.4 / diff / nxr@1.4
src/sys/arch/riscv/riscv/db_interface.c@1.4 / diff / nxr@1.4
src/sys/arch/riscv/riscv/ipifuncs.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/riscv/locore.S@1.43 / diff / nxr@1.43
src/sys/arch/riscv/riscv/pmap_machdep.c@1.19 / diff / nxr@1.19
src/sys/arch/riscv/riscv/riscv_machdep.c@1.34 / diff / nxr@1.34
src/sys/arch/riscv/riscv/riscv_tlb.c@1.2 / diff / nxr@1.2
Fix and enable MULTIPROCESSOR
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src/sys/arch/riscv/dev/plic.c@1.2
/
diff
/
nxr@1.2
src/sys/arch/riscv/dev/plic_fdt.c@1.3 / diff / nxr@1.3
src/sys/arch/riscv/dev/plicvar.h@1.2 / diff / nxr@1.2
src/sys/arch/riscv/dev/plic_fdt.c@1.3 / diff / nxr@1.3
src/sys/arch/riscv/dev/plicvar.h@1.2 / diff / nxr@1.2
Be clear about hart vs cpu. NFCI.
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Simplify plic_fdt_intr_disestablish by calling plic_intr_disestablish
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Fix a comment and enable RISC-V ddb mach commands
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Trailing whitespace.
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Remove duplicate .ci_cpl initialiser.
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risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache
Match other definitions of pmap_md_page_syncicache argument naming by
renaming the 2nd arg to 'onproc'
Match other definitions of pmap_md_page_syncicache argument naming by
renaming the 2nd arg to 'onproc'
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src/sys/arch/aarch64/include/pmap.h@1.59
/
diff
/
nxr@1.59
src/sys/arch/arm/include/arm32/pmap.h@1.176 / diff / nxr@1.176
src/sys/arch/arm/include/arm32/pmap.h@1.176 / diff / nxr@1.176
No need to define cpu_{,set}_tlb_info here - just use the
sys/uvm/pmap/pmap_tlb.h versions.
sys/uvm/pmap/pmap_tlb.h versions.
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Relax the TLB invalidation from full to by va for writing to kernel text
in db_write_text.
in db_write_text.
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Improve debug
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PR//57518: usb keyboard causes host controller to miss microframe
As per the USB 2.0 specification section 11.18.4; paragraph 3.b
For interrupt IN/OUT full-/low-speed transactions, the host must schedule a
complete-split transaction in each of the two microframes following the first
microframe in which the full-/low-speed transaction is budgeted. An additional
complete-split must also be scheduled in the third following microframe unless
the full-/low-speed transaction was budgeted to start in microframe Y6.
As per the USB 2.0 specification section 11.18.4; paragraph 3.b
For interrupt IN/OUT full-/low-speed transactions, the host must schedule a
complete-split transaction in each of the two microframes following the first
microframe in which the full-/low-speed transaction is budgeted. An additional
complete-split must also be scheduled in the third following microframe unless
the full-/low-speed transaction was budgeted to start in microframe Y6.
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Slight reformatting. NFCI.
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blank line audit
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src/sys/arch/aarch64/include/pmap_machdep.h@1.7
/
diff
/
nxr@1.7
src/sys/arch/riscv/include/pmap.h@1.19 / diff / nxr@1.19
src/sys/arch/riscv/include/pmap.h@1.19 / diff / nxr@1.19
G/C pmap_md_kernel_*
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Reduce #ifdefs
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Wrap long lines in a comment block.
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spaces to tabs.
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Remove debug printfs
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Trailing whitespace
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Attach the clock event counter for each cpu^Whart.
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src/sys/arch/hppa/hppa/genassym.cf@1.5
/
diff
/
nxr@1.5
src/sys/arch/hppa/hppa/trap.S@1.75 / diff / nxr@1.75
src/sys/arch/hppa/hppa/trap.c@1.122 / diff / nxr@1.122
src/sys/arch/hppa/include/proc.h@1.15 / diff / nxr@1.15
src/sys/arch/hppa/include/types.h@1.32 / diff / nxr@1.32
src/sys/arch/hppa/hppa/trap.S@1.75 / diff / nxr@1.75
src/sys/arch/hppa/hppa/trap.c@1.122 / diff / nxr@1.122
src/sys/arch/hppa/include/proc.h@1.15 / diff / nxr@1.15
src/sys/arch/hppa/include/types.h@1.32 / diff / nxr@1.32
PR/57261: hppa should be converted to __HAVE_SYSCALL_INTERN
Provide syscall_intern and use the md_syscall in syscall trap handling.
Provide syscall_intern and use the md_syscall in syscall trap handling.
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Use __BIT
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port-arm/57388: Minor bug fix in bcopy.S
Use correct register to check alignment of destination in backwards copy.
Patch from Antoni Pokusinski. Thanks.
Use correct register to check alignment of destination in backwards copy.
Patch from Antoni Pokusinski. Thanks.
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KASSERT -> KASSERTMSG
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src/lib/libc/arch/aarch64/SYS.h@1.4
/
diff
/
nxr@1.4
src/lib/libc/arch/arm/SYS.h@1.16 / diff / nxr@1.16
src/lib/libc/arch/arm/SYS.h@1.16 / diff / nxr@1.16
ENTRY / END indentation. NFCI.
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Indentation consistency. NFCI.
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USE __BIT() for CPUF_* flags. NFCI.
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riscv: Enable HEARTBEAT option in GENERIC.common
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G/C some #if 0 / #endif code
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Fix build when KERNHIST defined, but not UVMHIST
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G/C an unused struct cpu_info member
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Always initialise ci_tlb_info in cpu_info_store[0].
Fixes non-MP boot for me.
Fixes non-MP boot for me.
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Pad the trapframe so it's a multiple of 16 bytes so that when a trapframe
is created on the stack SP remains 16-byte aligned as per the ABI
requirements.
Patch from Rin with some updates from me.
is created on the stack SP remains 16-byte aligned as per the ABI
requirements.
Patch from Rin with some updates from me.
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G/C file was renamed in recent commit.
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src/sys/arch/riscv/conf/files.riscv@1.13
/
diff
/
nxr@1.13
src/sys/arch/riscv/fdt/cpu_fdt.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/fdt/intc_fdt.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/fdt/riscv_fdtvar.h@1.1 / diff / nxr@1.1
src/sys/arch/riscv/fdt/riscv_platform.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/include/cpu.h@1.12 / diff / nxr@1.12
src/sys/arch/riscv/include/db_machdep.h@1.8 / diff / nxr@1.8
src/sys/arch/riscv/include/intr.h@1.4 / diff / nxr@1.4
src/sys/arch/riscv/include/machdep.h@1.5 / diff / nxr@1.5
src/sys/arch/riscv/include/pmap.h@1.18 / diff / nxr@1.18
src/sys/arch/riscv/riscv/clock_machdep.c@1.5 / diff / nxr@1.5
src/sys/arch/riscv/riscv/cpu.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/riscv/cpu_subr.c@1.3 / diff / nxr@1.3
src/sys/arch/riscv/riscv/db_interface.c@1.3 / diff / nxr@1.3
src/sys/arch/riscv/riscv/db_machdep.c@1.11 / diff / nxr@1.11
src/sys/arch/riscv/riscv/genassym.cf@1.15 / diff / nxr@1.15
src/sys/arch/riscv/riscv/interrupt.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/riscv/ipifuncs.c@1.1 / diff / nxr@1.1
src/sys/arch/riscv/riscv/locore.S@1.42 / diff / nxr@1.42
src/sys/arch/riscv/riscv/pmap_machdep.c@1.18 / diff / nxr@1.18
:
(more 3 files)
src/sys/arch/riscv/fdt/cpu_fdt.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/fdt/intc_fdt.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/fdt/riscv_fdtvar.h@1.1 / diff / nxr@1.1
src/sys/arch/riscv/fdt/riscv_platform.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/include/cpu.h@1.12 / diff / nxr@1.12
src/sys/arch/riscv/include/db_machdep.h@1.8 / diff / nxr@1.8
src/sys/arch/riscv/include/intr.h@1.4 / diff / nxr@1.4
src/sys/arch/riscv/include/machdep.h@1.5 / diff / nxr@1.5
src/sys/arch/riscv/include/pmap.h@1.18 / diff / nxr@1.18
src/sys/arch/riscv/riscv/clock_machdep.c@1.5 / diff / nxr@1.5
src/sys/arch/riscv/riscv/cpu.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/riscv/cpu_subr.c@1.3 / diff / nxr@1.3
src/sys/arch/riscv/riscv/db_interface.c@1.3 / diff / nxr@1.3
src/sys/arch/riscv/riscv/db_machdep.c@1.11 / diff / nxr@1.11
src/sys/arch/riscv/riscv/genassym.cf@1.15 / diff / nxr@1.15
src/sys/arch/riscv/riscv/interrupt.c@1.2 / diff / nxr@1.2
src/sys/arch/riscv/riscv/ipifuncs.c@1.1 / diff / nxr@1.1
src/sys/arch/riscv/riscv/locore.S@1.42 / diff / nxr@1.42
src/sys/arch/riscv/riscv/pmap_machdep.c@1.18 / diff / nxr@1.18
:
(more 3 files)
risc-v: MULTIPROCESSOR support
Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.
Some other improvements to spl and cpu identification / reporting.
Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.
Some other improvements to spl and cpu identification / reporting.
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sort
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src/sys/arch/arm/fdt/cpus_fdt.c@1.1
/
diff
/
nxr@1.1
src/sys/arch/arm/fdt/files.fdt@1.35 / diff / nxr@1.35
src/sys/arch/riscv/fdt/cpus_fdt.c@1.1 / diff / nxr@1.1
src/sys/arch/riscv/fdt/files.fdt@1.2 / diff / nxr@1.2
src/sys/dev/fdt/cpus.c@1.8 / diff / nxr@1.8
src/sys/dev/fdt/fdtvar.h@1.79 / diff / nxr@1.79
src/sys/arch/arm/fdt/files.fdt@1.35 / diff / nxr@1.35
src/sys/arch/riscv/fdt/cpus_fdt.c@1.1 / diff / nxr@1.1
src/sys/arch/riscv/fdt/files.fdt@1.2 / diff / nxr@1.2
src/sys/dev/fdt/cpus.c@1.8 / diff / nxr@1.8
src/sys/dev/fdt/fdtvar.h@1.79 / diff / nxr@1.79
Call / define fdtbus_cpus_md_attach for platforms with cpus @ fdt.
The RISC-V binding here seems somewhat of an abuse, but it exists in
mainline linux.
The RISC-V binding here seems somewhat of an abuse, but it exists in
mainline linux.
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Fix compile for non-MULTIPROCESSOR and PMAP_TLB_MAX > 1 builds
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Fixup UVMHIST builds
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Remove magic numbers. NFCI.
Copyright maintenance while I'm here.
Copyright maintenance while I'm here.
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KASSERT(kpreempt_disabled()) before accessing curcpu() to reflect why
preemption needs to be disabled more clearly.
preemption needs to be disabled more clearly.
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Trailing whitespace.
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Whitespace.
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Second arg to fdt_memory_remove_range is a size so pass dtbsize and not
dtb + dtbsize
dtb + dtbsize
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Fix CLKF_INTR so that not all time is shown as being spent in interrupts.
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Fix a comment
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src/lib/libc/compat/arch/riscv/Makefile.inc@1.2
/
diff
/
nxr@1.2
src/lib/libc/compat/arch/riscv/sys/Makefile.inc@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_Ovfork.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_msgctl.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_quotactl.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_shmctl.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigaction.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigpending.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigprocmask.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigreturn.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigsuspend.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/Makefile.inc@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_Ovfork.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_msgctl.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_quotactl.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_shmctl.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigaction.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigpending.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigprocmask.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigreturn.S@1.1 / diff / nxr@1.1
src/lib/libc/compat/arch/riscv/sys/compat_sigsuspend.S@1.1 / diff / nxr@1.1
Add the compat calls for renamed symbols so that configure scripts
can find them. sigprocmask being the most problematic.
RISC-V doesn't need the compat syscalls, but seeing them fail in
ktrace is helpful.
can find them. sigprocmask being the most problematic.
RISC-V doesn't need the compat syscalls, but seeing them fail in
ktrace is helpful.
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No need for double semi-colon
Indent END the same as ENTRY.
NFCI.
Indent END the same as ENTRY.
NFCI.
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Check for RB_HALT in cpu_reboot.
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risc-v: use ${MACHINE}-${MACHINE_ARCH} for the default RELEASEMACHINEDIR
Hopefully, this fixes the release binaries being available on cdn/nyftp.
Hopefully, this fixes the release binaries being available on cdn/nyftp.
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RISC-V: enabled GDB
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src/external/gpl3/gdb.old/lib/libbfd/Makefile@1.12
/
diff
/
nxr@1.12
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/bfd-in3.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/bfd.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/bfd_stdint.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/bfdver.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/targmatch.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/bfd-in3.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/bfd.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/bfd_stdint.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/bfdver.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/targmatch.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libctf/arch/riscv32/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libctf/arch/riscv32/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libctf/arch/riscv64/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libctf/arch/riscv64/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libdecnumber/arch/riscv32/config.h@1.1 / diff / nxr@1.1
:
(more 75 files)
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/bfd-in3.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/bfd.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/bfd_stdint.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/bfdver.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv32/targmatch.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/bfd-in3.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/bfd.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/bfd_stdint.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/bfdver.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libbfd/arch/riscv64/targmatch.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libctf/arch/riscv32/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libctf/arch/riscv32/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libctf/arch/riscv64/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libctf/arch/riscv64/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb.old/lib/libdecnumber/arch/riscv32/config.h@1.1 / diff / nxr@1.1
:
(more 75 files)
RISC-V mknative and build support for gdb.old
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src/external/gpl3/gdb/lib/libbfd/Makefile@1.14
/
diff
/
nxr@1.14
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/bfd-in3.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/bfd.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/bfd_stdint.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/bfdver.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/targmatch.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/bfd-in3.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/bfd.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/bfd_stdint.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/bfdver.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/targmatch.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libctf/arch/riscv32/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libctf/arch/riscv32/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libctf/arch/riscv64/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libctf/arch/riscv64/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libdecnumber/arch/riscv32/config.h@1.1 / diff / nxr@1.1
:
(more 75 files)
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/bfd-in3.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/bfd.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/bfd_stdint.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/bfdver.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv32/targmatch.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/bfd-in3.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/bfd.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/bfd_stdint.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/bfdver.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libbfd/arch/riscv64/targmatch.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libctf/arch/riscv32/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libctf/arch/riscv32/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libctf/arch/riscv64/config.h@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libctf/arch/riscv64/defs.mk@1.1 / diff / nxr@1.1
src/external/gpl3/gdb/lib/libdecnumber/arch/riscv32/config.h@1.1 / diff / nxr@1.1
:
(more 75 files)
RISC-V mknative and build support.
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Don't expose vaddr_t or register_t to userland. The gdb configure script
needs this so it can detect struct lwp correctly.
needs this so it can detect struct lwp correctly.
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Google goldfish config goop
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Set ac_cv_func_sigprocmask=yes as the symbol renaming confuses the
configure script on architectures that don't provide a compatibilty
symbol, e.g. RISC-V
configure script on architectures that don't provide a compatibilty
symbol, e.g. RISC-V
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Ugly hack to fix the builds.
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Remove some #if 0'ed code