Sun Dec 29 09:40:59 2019 UTC ()
Pull up following revision(s) (requested by jmcneill in ticket #589):

	sys/arch/arm/include/cputypes.h: revision 1.11
	sys/arch/aarch64/aarch64/cpu.c: revision 1.31

Identify Arm Neoverse E1 and N1 CPUs.


(martin)
diff -r1.20.2.1 -r1.20.2.2 src/sys/arch/aarch64/aarch64/cpu.c
diff -r1.8 -r1.8.2.1 src/sys/arch/arm/include/cputypes.h
cvs diff -r1.20.2.1 -r1.20.2.2 src/sys/arch/aarch64/aarch64/cpu.c (expand / switch to unified diff)

--- src/sys/arch/aarch64/aarch64/cpu.c 2019/10/23 19:14:19 1.20.2.1
+++ src/sys/arch/aarch64/aarch64/cpu.c 2019/12/29 09:40:59 1.20.2.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpu.c,v 1.20.2.1 2019/10/23 19:14:19 martin Exp $ */ 1/* $NetBSD: cpu.c,v 1.20.2.2 2019/12/29 09:40:59 martin Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org> 4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -17,27 +17,27 @@ @@ -17,27 +17,27 @@
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE. 26 * POSSIBILITY OF SUCH DAMAGE.
27 */ 27 */
28 28
29#include <sys/cdefs.h> 29#include <sys/cdefs.h>
30__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.20.2.1 2019/10/23 19:14:19 martin Exp $"); 30__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.20.2.2 2019/12/29 09:40:59 martin Exp $");
31 31
32#include "locators.h" 32#include "locators.h"
33#include "opt_arm_debug.h" 33#include "opt_arm_debug.h"
34#include "opt_fdt.h" 34#include "opt_fdt.h"
35#include "opt_multiprocessor.h" 35#include "opt_multiprocessor.h"
36 36
37#include <sys/param.h> 37#include <sys/param.h>
38#include <sys/systm.h> 38#include <sys/systm.h>
39#include <sys/atomic.h> 39#include <sys/atomic.h>
40#include <sys/device.h> 40#include <sys/device.h>
41#include <sys/cpu.h> 41#include <sys/cpu.h>
42#include <sys/kmem.h> 42#include <sys/kmem.h>
43#include <sys/reboot.h> 43#include <sys/reboot.h>
@@ -186,26 +186,28 @@ struct cpuidtab { @@ -186,26 +186,28 @@ struct cpuidtab {
186const struct cpuidtab cpuids[] = { 186const struct cpuidtab cpuids[] = {
187 { CPU_ID_CORTEXA35R0 & CPU_PARTMASK, "Cortex-A35", "Cortex", "V8-A" }, 187 { CPU_ID_CORTEXA35R0 & CPU_PARTMASK, "Cortex-A35", "Cortex", "V8-A" },
188 { CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Cortex", "V8-A" }, 188 { CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Cortex", "V8-A" },
189 { CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Cortex", "V8-A" }, 189 { CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Cortex", "V8-A" },
190 { CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Cortex", "V8.2-A+" }, 190 { CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Cortex", "V8.2-A+" },
191 { CPU_ID_CORTEXA65R0 & CPU_PARTMASK, "Cortex-A65", "Cortex", "V8.2-A+" }, 191 { CPU_ID_CORTEXA65R0 & CPU_PARTMASK, "Cortex-A65", "Cortex", "V8.2-A+" },
192 { CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Cortex", "V8-A" }, 192 { CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Cortex", "V8-A" },
193 { CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Cortex", "V8-A" }, 193 { CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Cortex", "V8-A" },
194 { CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A+" }, 194 { CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A+" },
195 { CPU_ID_CORTEXA76R3 & CPU_PARTMASK, "Cortex-A76", "Cortex", "V8.2-A+" }, 195 { CPU_ID_CORTEXA76R3 & CPU_PARTMASK, "Cortex-A76", "Cortex", "V8.2-A+" },
196 { CPU_ID_CORTEXA76AER1 & CPU_PARTMASK, "Cortex-A76AE", "Cortex", "V8.2-A+" }, 196 { CPU_ID_CORTEXA76AER1 & CPU_PARTMASK, "Cortex-A76AE", "Cortex", "V8.2-A+" },
197 { CPU_ID_CORTEXA77R0 & CPU_PARTMASK, "Cortex-A77", "Cortex", "V8.2-A+" }, 197 { CPU_ID_CORTEXA77R0 & CPU_PARTMASK, "Cortex-A77", "Cortex", "V8.2-A+" },
198 { CPU_ID_EMAG8180 & CPU_PARTMASK, "Ampere eMAG", "Skylark", "V8-A" }, 198 { CPU_ID_EMAG8180 & CPU_PARTMASK, "Ampere eMAG", "Skylark", "V8-A" },
 199 { CPU_ID_NEOVERSEE1R1 & CPU_PARTMASK, "Neoverse E1", "Neoverse", "V8.2-A+" },
 200 { CPU_ID_NEOVERSEN1R3 & CPU_PARTMASK, "Neoverse N1", "Neoverse", "V8.2-A+" },
199 { CPU_ID_THUNDERXRX, "Cavium ThunderX", "Cavium", "V8-A" }, 201 { CPU_ID_THUNDERXRX, "Cavium ThunderX", "Cavium", "V8-A" },
200 { CPU_ID_THUNDERX81XXRX, "Cavium ThunderX CN81XX", "Cavium", "V8-A" }, 202 { CPU_ID_THUNDERX81XXRX, "Cavium ThunderX CN81XX", "Cavium", "V8-A" },
201 { CPU_ID_THUNDERX83XXRX, "Cavium ThunderX CN83XX", "Cavium", "V8-A" }, 203 { CPU_ID_THUNDERX83XXRX, "Cavium ThunderX CN83XX", "Cavium", "V8-A" },
202 { CPU_ID_THUNDERX2RX, "Cavium ThunderX2", "Cavium", "V8.1-A" }, 204 { CPU_ID_THUNDERX2RX, "Cavium ThunderX2", "Cavium", "V8.1-A" },
203}; 205};
204 206
205static void 207static void
206identify_aarch64_model(uint32_t cpuid, char *buf, size_t len) 208identify_aarch64_model(uint32_t cpuid, char *buf, size_t len)
207{ 209{
208 int i; 210 int i;
209 uint32_t cpupart, variant, revision; 211 uint32_t cpupart, variant, revision;
210 212
211 cpupart = cpuid & CPU_PARTMASK; 213 cpupart = cpuid & CPU_PARTMASK;
cvs diff -r1.8 -r1.8.2.1 src/sys/arch/arm/include/cputypes.h (expand / switch to unified diff)

--- src/sys/arch/arm/include/cputypes.h 2019/07/16 10:37:12 1.8
+++ src/sys/arch/arm/include/cputypes.h 2019/12/29 09:40:59 1.8.2.1
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cputypes.h,v 1.8 2019/07/16 10:37:12 jmcneill Exp $ */ 1/* $NetBSD: cputypes.h,v 1.8.2.1 2019/12/29 09:40:59 martin Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1998, 2001 Ben Harris 4 * Copyright (c) 1998, 2001 Ben Harris
5 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994-1996 Mark Brinicombe.
6 * Copyright (c) 1994 Brini. 6 * Copyright (c) 1994 Brini.
7 * All rights reserved. 7 * All rights reserved.
8 * 8 *
9 * This code is derived from software written for Brini by Mark Brinicombe 9 * This code is derived from software written for Brini by Mark Brinicombe
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -162,26 +162,28 @@ @@ -162,26 +162,28 @@
162#define CPU_ID_CORTEXA32R1 0x411fd010 162#define CPU_ID_CORTEXA32R1 0x411fd010
163#define CPU_ID_CORTEXA35R0 0x410fd040 163#define CPU_ID_CORTEXA35R0 0x410fd040
164#define CPU_ID_CORTEXA35R1 0x411fd040 164#define CPU_ID_CORTEXA35R1 0x411fd040
165#define CPU_ID_CORTEXA53R0 0x410fd030 165#define CPU_ID_CORTEXA53R0 0x410fd030
166#define CPU_ID_CORTEXA55R1 0x411fd050 166#define CPU_ID_CORTEXA55R1 0x411fd050
167#define CPU_ID_CORTEXA57R0 0x410fd070 167#define CPU_ID_CORTEXA57R0 0x410fd070
168#define CPU_ID_CORTEXA57R1 0x411fd070 168#define CPU_ID_CORTEXA57R1 0x411fd070
169#define CPU_ID_CORTEXA65R0 0x410fd060 169#define CPU_ID_CORTEXA65R0 0x410fd060
170#define CPU_ID_CORTEXA72R0 0x410fd080 170#define CPU_ID_CORTEXA72R0 0x410fd080
171#define CPU_ID_CORTEXA73R0 0x410fd090 171#define CPU_ID_CORTEXA73R0 0x410fd090
172#define CPU_ID_CORTEXA75R2 0x412fd0a0 172#define CPU_ID_CORTEXA75R2 0x412fd0a0
173#define CPU_ID_CORTEXA76AER1 0x411fd0e0 173#define CPU_ID_CORTEXA76AER1 0x411fd0e0
174#define CPU_ID_CORTEXA76R3 0x413fd0b0 174#define CPU_ID_CORTEXA76R3 0x413fd0b0
 175#define CPU_ID_NEOVERSEN1R3 0x413fd0c0
 176#define CPU_ID_NEOVERSEE1R1 0x411fd4a0
175#define CPU_ID_CORTEXA77R0 0x410fd0d0 177#define CPU_ID_CORTEXA77R0 0x410fd0d0
176 178
177#define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000) 179#define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000)
178#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) 180#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050)
179#define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) 181#define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070)
180#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) 182#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
181#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) 183#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
182#define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) 184#define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0)
183#define CPU_ID_CORTEX_A32_P(n) ((n & 0xff0ff0f0) == 0x410fd010) 185#define CPU_ID_CORTEX_A32_P(n) ((n & 0xff0ff0f0) == 0x410fd010)
184#define CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040) 186#define CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040)
185#define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030) 187#define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030)
186#define CPU_ID_CORTEX_A55_P(n) ((n & 0xff0ff0f0) == 0x410fd050) 188#define CPU_ID_CORTEX_A55_P(n) ((n & 0xff0ff0f0) == 0x410fd050)
187#define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070) 189#define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070)