 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_cemac.c,v 1.21 2019/05/28 07:41:48 msaitoh Exp $	*/
+/*	$NetBSD: if_cemac.c,v 1.22 2020/01/29 05:54:29 thorpej Exp $	*/
 /*
  * Copyright (c) 2015  Genetec Corporation.  All rights reserved.
  * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
  * Based on arch/arm/at91/at91emac.c
+ *
  * Copyright (c) 2007 Embedtronics Oy
  * All rights reserved.
+ *
  * Copyright (c) 2004 Jesse Off
  * All rights reserved.
+ *
 @@ -30,27 +30,27 @@
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Cadence EMAC/GEM ethernet controller IP driver
  * used by arm/at91, arm/zynq SoC
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.21 2019/05/28 07:41:48 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.22 2020/01/29 05:54:29 thorpej Exp $");
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/ioctl.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/malloc.h>
 #include <sys/time.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <sys/bus.h>
 @@ -286,40 +286,41 @@ cemac_intr(void *arg)
 	    ETH_ISR_RBNA | ETH_ISR_ROVR | ETH_ISR_TCOM))) {
 		// interrupt not enabled, can't be us
 		return 0;
+	}
 	isr = CEMAC_READ(ETH_ISR);
 	CEMAC_WRITE(ETH_ISR, isr);
 	isr &= imr;
 #ifdef	CEMAC_DEBUG
 	rsr = CEMAC_READ(ETH_RSR);		// get receive status register
 #endif
 	DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, isr, rsr, imr));
 	net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
 	if (isr & ETH_ISR_RBNA) {		// out of receive buffers
 		CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA);	// clear interrupt
 		ctl = CEMAC_READ(ETH_CTL);		// get current control register value
 		CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);	// disable receiver
 		CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA);	// clear BNA bit
 		CEMAC_WRITE(ETH_CTL, ctl |  ETH_CTL_RE);	// re-enable receiver
-		ifp->if_ierrors++;
+		if_statinc_ref(nsr, if_ierrors);
-		ifp->if_ipackets++;
+		if_statinc_ref(nsr, if_ipackets);
 		DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__));
+	}
 	if (isr & ETH_ISR_ROVR) {
 		CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR);	// clear interrupt
-		ifp->if_ierrors++;
+		if_statinc_ref(nsr, if_ierrors);
-		ifp->if_ipackets++;
+		if_statinc_ref(nsr, if_ipackets);
 		DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__));
+	}
 	if (isr & ETH_ISR_RCOM) {			// packet has been received!
 		uint32_t nfo;
 		DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info));
 		while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) {
 			int fl, csum;
 			struct mbuf *m;
 			nfo = sc->RDSC[bi].Info;
 			fl = (nfo & ETH_RDSC_I_LEN) - 4;
 			DPRINTFN(2,("## nfo=0x%08X\n", nfo));
 @@ -363,32 +364,34 @@ cemac_intr(void *arg)
 					NULL, BUS_DMA_NOWAIT);
 				bus_dmamap_sync(sc->sc_dmat, sc->rxq[bi].m_dmamap, 0,
 						MCLBYTES, BUS_DMASYNC_PREREAD);
 				sc->RDSC[bi].Info = 0;
 				sc->RDSC[bi].Addr =
 					sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr
 					| (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0);
 			} else {
 				/* Drop packets until we can get replacement
 				 * empty mbufs for the RXDQ.
 				 */
 				if (m != NULL)
 					m_freem(m);
-				ifp->if_ierrors++;
+				if_statinc_ref(nsr, if_ierrors);
+			}
 			sc->rxqi++;
+		}
+	}
 	IF_STAT_PUTREF(ifp);
 	if (cemac_gctx(sc) > 0)
 		if_schedule_deferred_start(ifp);
 #if 0 // reloop
 	irq = CEMAC_READ(IntStsC);
 	if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0)
 		goto begin;
 #endif
 	return (1);
+}
 static void
 @@ -709,29 +712,31 @@ cemac_statchg(struct ifnet *ifp)
 		break;
+	}
 	CEMAC_WRITE(ETH_CFG, reg);
+}
 static void
 cemac_tick(void *arg)
+{
 	struct cemac_softc* sc = (struct cemac_softc *)arg;
 	struct ifnet * ifp = &sc->sc_ethercom.ec_if;
 	int s;
 	if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM))
-		ifp->if_collisions += CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL);
+		if_statadd(ifp, if_collisions,
 		    CEMAC_READ(GEM_SCOL) + CEMAC_READ(GEM_MCOL));
 	else
-		ifp->if_collisions += CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL);
+		if_statadd(ifp, if_collisions,
 		    CEMAC_READ(ETH_SCOL) + CEMAC_READ(ETH_MCOL));
 	/* These misses are ok, they will happen if the RAM/CPU can't keep up */
 	if (!ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) {
 		uint32_t misses = CEMAC_READ(ETH_DRFC);
 		if (misses > 0)
 			aprint_normal_ifnet(ifp, "%d rx misses\n", misses);
+	}
 	s = splnet();
 	if (cemac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0)
 		cemac_ifstart(ifp);
 	splx(s);