 @@ -1,23 +1,23 @@
-/* $NetBSD: cycv_platform.c,v 1.15 2020/11/27 07:11:49 skrll Exp $ */
+/* $NetBSD: cycv_platform.c,v 1.16 2021/01/29 13:10:07 rin Exp $ */
 /* This file is in the public domain. */
 #include "arml2cc.h"
 #include "opt_console.h"
 #include "opt_multiprocessor.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.15 2020/11/27 07:11:49 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.16 2021/01/29 13:10:07 rin Exp $");
 #define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <arm/arm32/machdep.h>
 #include <arm/altera/cycv_reg.h>
 #include <arm/altera/cycv_var.h>
 @@ -69,30 +69,32 @@ cycv_platform_bootstrap(void)
 	bus_space_map(bst, CYCV_L2CACHE_BASE, CYCV_L2CACHE_SIZE, 0, &bsh_l2c);
 #if NARML2CC > 0
 	arml2cc_init(bst, bsh_l2c, 0);
 #endif
 	arm_fdt_cpu_bootstrap();
+}
 static int
 cycv_mpstart(void)
+{
 	int ret = 0;
 #ifdef MULTIPROCESSOR
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh_rst;
 	bus_space_handle_t bsh_scu;
 	int ret = 0;
 	bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh_rst);
 	bus_space_map(bst, CYCV_SCU_BASE, CYCV_SCU_SIZE, 0, &bsh_scu);
 	/* Enable Snoop Control Unit */
 	bus_space_write_4(bst, bsh_scu, SCU_INV_ALL_REG, 0xff);
 	bus_space_write_4(bst, bsh_scu, SCU_CTL,
 		bus_space_read_4(bst, bsh_scu, SCU_CTL) | SCU_CTL_SCU_ENA);
 	const uint32_t startfunc =
 		(uint32_t) KERN_VTOPHYS((vaddr_t) cpu_mpstart);
 	/*
 @@ -113,26 +115,27 @@ cycv_mpstart(void)
 		bus_space_read_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST) &
 			~CYCV_RSTMGR_MPUMODRST_CPU1);
 	/* Wait for secondary processor to start */
 	int i;
 	for (i = 0x10000000; i > 0; i--) {
 		if (cpu_hatched_p(1))
 			break;
+	}
 	if (i == 0) {
 		aprint_error("cpu%d: WARNING: AP failed to start\n", 1);
 		ret++;
+	}
 #endif
 	return ret;
+}
 static void
 cycv_platform_init_attach_args(struct fdt_attach_args *faa) {
 	faa->faa_bst = &armv7_generic_bs_tag;
 	faa->faa_dmat = &arm_generic_dma_tag;
+}
 static void
 cycv_platform_device_register(device_t dev, void *aux) {
 	prop_dictionary_t dict = device_properties(dev);

 @@ -1,14 +1,14 @@
-/* $NetBSD: meson_platform.c,v 1.16 2020/09/28 11:54:22 jmcneill Exp $ */
+/* $NetBSD: meson_platform.c,v 1.17 2021/01/29 13:10:07 rin Exp $ */
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -23,27 +23,27 @@
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_soc.h"
 #include "opt_multiprocessor.h"
 #include "opt_console.h"
 #include "arml2cc.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.16 2020/09/28 11:54:22 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_platform.c,v 1.17 2021/01/29 13:10:07 rin Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/termios.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <uvm/uvm_extern.h>
 #include <machine/bootconfig.h>
 @@ -309,36 +309,39 @@ meson8b_platform_reset(void)
 	bus_space_handle_t bsh;
 	bus_space_map(bst, MESON8B_WATCHDOG_BASE, MESON8B_WATCHDOG_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_TC,
 	    MESON8B_WATCHDOG_TC_CPUS | MESON8B_WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, MESON8B_WATCHDOG_TC_TCNT));
 	bus_space_write_4(bst, bsh, MESON8B_WATCHDOG_RESET, 0);
 	for (;;) {
 		__asm("wfi");
+	}
+}
 #ifdef MULTIPROCESSOR
 static void
 meson8b_mpinit_delay(u_int n)
+{
 	for (volatile int i = 0; i < n; i++)
+		;
+}
 #endif
 static int
 cpu_enable_meson8b(int phandle)
+{
 #ifdef MULTIPROCESSOR
 	const bus_addr_t cbar = armreg_cbar_read();
 	bus_space_tag_t bst = &arm_generic_bs_tag;
 	const bus_space_handle_t scu_bsh =
 	    cbar - MESON8B_ARM_PBASE + MESON8B_ARM_VBASE;
 	const bus_space_handle_t cpuconf_bsh =
 	    MESON8B_SRAM_VBASE + MESON8B_SRAM_CPUCONF_OFFSET;
 	const bus_space_handle_t ao_bsh =
 	    MESON8B_AOBUS_VBASE + MESON8B_AOBUS_RTI_OFFSET;
 	const bus_space_handle_t cbus_bsh =
 	    MESON_CORE_APB3_VBASE + MESON_CBUS_OFFSET;
 	uint32_t pwr_sts, pwr_cntl0, pwr_cntl1, cpuclk, mempd0;
 	uint64_t mpidr;
 @@ -386,26 +389,27 @@ cpu_enable_meson8b(int phandle)
 	pwr_cntl0 &= ~(1 << cpuno);
 	bus_space_write_4(bst, ao_bsh, MESON_AOBUS_PWR_CTRL0_REG, pwr_cntl0);
 	cpuclk = bus_space_read_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG);
 	cpuclk &= ~(1 << (24 + cpuno));
 	bus_space_write_4(bst, cbus_bsh, MESON_CBUS_CPU_CLK_CNTL_REG, cpuclk);
 	bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CPU_ADDR_REG(cpuno),
 	    KERN_VTOPHYS((vaddr_t)cpu_mpstart));
 	uint32_t ctrl = bus_space_read_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG);
 	ctrl |= __BITS(cpuno,0);
 	bus_space_write_4(bst, cpuconf_bsh, MESON8B_SRAM_CPUCONF_CTRL_REG, ctrl);
 #endif
 	return 0;
+}
 ARM_CPU_METHOD(meson8b, "amlogic,meson8b-smp", cpu_enable_meson8b);
 static int
 meson8b_mpstart(void)
+{
 	int ret = 0;
 	const bus_addr_t cbar = armreg_cbar_read();
 	bus_space_tag_t bst = &arm_generic_bs_tag;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: imx6_platform.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $	*/
+/*	$NetBSD: imx6_platform.c,v 1.3 2021/01/29 13:10:07 rin Exp $	*/
 /*-
  * Copyright (c) 2019 Genetec Corporation.  All rights reserved.
  * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_platform.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_platform.c,v 1.3 2021/01/29 13:10:07 rin Exp $");
 #include "arml2cc.h"
 #include "opt_console.h"
 #include "opt_fdt.h"
 #include "opt_multiprocessor.h"
 #include "opt_soc.h"
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/termios.h>
 @@ -181,26 +181,28 @@ imx_platform_mpstart(void)
 	    SRC_SCR_CORE3_ENABLE);
 	bus_space_write_4(bst, bsh, SRC_SCR, srcctl);
 	for (int i = 1; i < arm_cpu_max; i++) {
 		bus_space_write_4(bst, bsh, SRC_GPRN_ENTRY(i), mpstart);
 		srcctl |= SRC_SCR_COREN_RST(i);
 		srcctl |= SRC_SCR_COREN_ENABLE(i);
+	}
 	bus_space_write_4(bst, bsh, SRC_SCR, srcctl);
 	bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE);
 	return arm_fdt_cpu_mpstart();
 #else
 	return 0;
 #endif
+}
 static void
 imx6_platform_reset(void)
+{
 	bus_space_tag_t bst = &armv7_generic_bs_tag;
 	bus_space_handle_t bsh;
 	if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_WDOG1_BASE, AIPS1_WDOG_SIZE, 0, &bsh))
 		panic("couldn't map wdog1 registers");
 	delay(1000);	/* wait for flushing FIFO of serial console */

 @@ -1,14 +1,14 @@
-/* $NetBSD: ti_gpio.c,v 1.11 2021/01/29 13:07:32 rin Exp $ */
+/* $NetBSD: ti_gpio.c,v 1.12 2021/01/29 13:10:07 rin Exp $ */
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,35 +17,36 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.11 2021/01/29 13:07:32 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.12 2021/01/29 13:10:07 rin Exp $");
 #include <sys/param.h>
 #include <sys/bitops.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/gpio.h>
 #include <sys/intr.h>
 #include <sys/kmem.h>
 #include <sys/lwp.h>
 #include <sys/mutex.h>
 #include <sys/systm.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/gpio/gpiovar.h>
 #include <arm/ti/ti_prcm.h>
 #define	TI_GPIO_NPINS			32
 enum ti_gpio_type {
 	TI_GPIO_OMAP3,
 	TI_GPIO_OMAP4,